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OCR H446 1.2.1 Interrupts, ISR and the FDE cycle

Part 4 of 12 · H446 1.2.1 · Systems software

Interrupt answers in H446 1.2.1 usually go wrong on ordering, so this worksheet rebuilds the sequence around the fetch, decode and execute cycle: the check happens at an instruction boundary, register state is saved to the stack, the service routine runs, then the interrupted program resumes exactly where it stopped.

Students will:

  • distinguish the interrupt signal from the interrupt service routine that deals with it
  • place the priority check at the correct point in the instruction cycle
  • explain why register values are saved before the service routine runs
  • explain how the stack makes nested interrupt handling possible
  • correct the claim that an interrupt is handled part-way through an instruction

Inside: 4 explanation cells, 5 multiple-choice questions, 3 fill-in-the-blanks cells and 3 written answers. 32 marks, about 40 to 50 minutes.

Series: H446 1.2.1 · Systems software, part 4 of 12.

Shared by Coding PathwayVerified teacher

  • 15 cells
  • About 45 minutes
  • CC BY-SA 4.0
  • Shared 31 Aug 2026
  • Updated 3 Sept 2026

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Interrupts, ISR and the FDE cycle

While the processor repeatedly fetches, decodes and executes program instructions, devices and software sometimes need its attention. An interrupt is a signal that requests attention. An interrupt service routine (ISR) is the program that deals with the event.

You should already know: the program counter stores the address of the next instruction and registers hold the current processor state.

Worked model: pause without losing the program

Interrupt handling sequencefinish currentinstruction cyclecheck interruptand prioritysave registersto the stackset PC to ISRand service itrestore stateand resumean interrupt is a signal; the ISR is the program that handles itA lower-priority request can wait. Saving and restoring state lets the interrupted program continue correctly.The ISR instructions themselves are fetched, decoded and executed like other program instructions.

The processor does not normally abandon an instruction halfway through. At a cycle boundary it checks pending interrupts and their priorities. If a request is accepted, the current register values are pushed onto a stack so the program's exact state can be recovered.

The program counter is changed to the first instruction of the ISR. The ISR is fetched, decoded and executed. When it finishes, the saved register values are restored and the original program resumes.

Multiple choice1 mark

Which statement correctly distinguishes an interrupt from an ISR?

  • AThe interrupt is a program; the ISR is a processor register
  • BThey are two names for the same hardware wire
  • CThe ISR signals that the processor needs attention
  • DThe interrupt is a signal; the ISR is the program that handles its cause
Fill in the blanks5 marks
Complete the examples of interrupt sources.
Source categoryExample
Hardwarepower or reset entry 1
User inputkeyboard entry 2
Softwareillegal instruction or arithmetic entry 3
Timera scheduled sensor entry 4
Input/outputcompletion of a data entry 5
Multiple choice1 mark

When does the CPU normally check whether a pending interrupt should be handled?

  • AAt the start or end of a fetch-decode-execute cycle
  • BHalfway through every instruction
  • COnly when the operating system is installed
  • DAfter the computer is switched off
Fill in the blanks6 marks
Complete the handling sequence: finish the current instruction cycle; check the request and its entry 1; save register values to the entry 2; change the entry 3 counter to the ISR address; run the entry 4; restore the saved entry 5; resume the interrupted entry 6.
Multiple choice1 mark

Why are register values saved before the ISR runs?

  • ATo make secondary storage faster
  • BSo the interrupted program can resume from the same processor state
  • CSo the ISR can permanently replace the original program
  • DTo clear the operating system from RAM
Written answer6 marks

Explain how the CPU handles a higher-priority interrupt and then returns to the original program.

Write the stages in a logical order and use PC, stack and ISR accurately.

Students type their answer here.

Multiple choice1 mark

A low-priority printer-status interrupt is pending while a higher-priority power-failure ISR is running. What is the most accurate outcome?

  • AThe printer request must immediately replace the power-failure ISR
  • BBoth ISRs are combined into one instruction
  • CThe lower-priority request can remain pending until the higher-priority service has completed
  • DThe printer request permanently deletes the saved register state
Written answer3 marks

While ISR A is running, a higher-priority interrupt B is accepted. Explain how the stack makes nested interrupt handling possible.

Describe saving A, handling B and returning in the correct order.

Students type their answer here.

Written answer3 marks

Correct this statement: ‘As soon as a key is pressed, the CPU immediately runs the interrupt in the middle of its current instruction.’

Identify two separate errors and replace them with the correct mechanism.

Students type their answer here.

Multiple choice1 mark

How are the instructions inside an ISR processed?

  • AThey bypass the fetch-decode-execute cycle
  • BThey are handled only by secondary storage
  • CThey are converted into interrupts before execution
  • DThey are fetched, decoded and executed like other program instructions

Closed-book checkpoint

Complete the method from memory. No answer bank is provided.

Fill in the blanks4 marks
A request for processor attention is an entry 1. The routine that responds is separate executable entry 2. Preserving the current CPU context allows later entry 3, while ordering requests by urgency prevents a minor event displacing a more entry 4 one.

Review your understanding

Before submitting, check that you can explain the main distinction in your own words, apply it in an unfamiliar context and justify each consequence rather than only naming a feature.