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Types of processor examination transition

Complete this worksheet closed-book and without checking answers as you go. All contexts, values and wording are original; the questions target matched comparison, workload analysis and conditional performance reasoning.

Multiple choice1 mark

Which is a full CISC/RISC comparison?

ACISC has more modes and RISC uses less energy
BCISC typically has more addressing modes, whereas RISC typically has fewer
CRISC is fast and CISC is complex
DCISC is for desktops

Written answer6 marks

Compare three differences between CISC and RISC. Discuss the same feature for both processor types in each comparison. State when any cycle, pipeline or performance claim may not apply.

Choose from instruction set/form, hardware/compiler, cycles, code/RAM, energy, addressing or pipeline suitability.

Students type their answer here.

Written answer6 marks

A handheld maintenance terminal needs long battery life but must access an established application built for a different instruction-set platform. Discuss CISC and RISC consequences and justify a processor route.

Apply energy/cooling/size and software compatibility/migration; either conclusion can be defended.

Students type their answer here.

Written answer8 marks

Recommend CPU, GPU or mixed processing for each workload. Give one workload-based reason for every choice.

Independent colour transforms for millions of pixels.
A short, branch-heavy safety controller.
Repeated matrix operations plus varied program coordination.
A large but strictly dependent record sequence.

Use similarity, independence, branching and coordination.

Students type their answer here.

Written answer6 marks

Explain two benefits of using a GPU for real-time scientific visualisation and one non-graphics GPU use. Connect specialist instructions/many processing units/SIMD to the result.

Generic ‘GPU is faster’ is insufficient.

Students type their answer here.

Fill in the blanks4 marks

A processor package with several processing gap 1 is multicore. Parallel processing divides work across multiple units when tasks are sufficiently gap 2. Pipelining overlaps different instructions across FDE gap 3. A serial dependency causes gap 4 rather than useful overlap.

cores
independent
stages
waiting
storage

Written answer5 marks

A job has stages A → (B, C, D) → E. Describe a valid two-core schedule, then explain why doubling to four cores does not halve total time. Include dependencies and one overhead or system bottleneck.

A and E are serial; B/C/D are independent after A.

Students type their answer here.

Written answer5 marks

Explain three reasons why a multicore processor may not improve one application, and one benefit when several independent programs run at the same time.

Include task, software and system angles.

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Written answer9 marks

A research vehicle has a low-power control computer, several cameras, a GPU and a four-core CPU. Discuss how the available processor types should be used. Your answer should consider:

control and existing software;
image processing and modelling;
CISC/RISC trade-offs;
CPU/GPU workload shape;
multicore and parallel-processing limits.

Reach a justified overall design decision.

Integrate the system. Explain how each choice fits the workload and state important limitations instead of listing definitions.

Students type their answer here.

Review your responses

Check that each CISC/RISC comparison discusses the same feature on both sides, each CPU/GPU choice follows from workload shape, and every multicore claim accounts for dependencies, serial work and bottlenecks. Rework any answer that gives only a processor label without explaining how the effect occurs.