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OCR H446 1.4.3 D-type flip-flops

Part 9 of 11 · H446 1.4.3 · Boolean algebra

Every other circuit in OCR H446 1.4.3 calculates an output from its current inputs; a D-type flip-flop stores one bit over time. This worksheet covers clock-edge sampling, the held output between edges, and, just as usefully for revision, where the required knowledge stops.

Students will:

  • explain that the output copies the D input only at an active clock edge
  • state what the output does when D changes between two edges
  • describe how several flip-flops together hold a multi-bit value in a register
  • compare a circuit that stores state with one that only combines current inputs
  • recognise which electronics detail sits outside the required H446 knowledge

Inside: 5 explanation cells, 3 multiple-choice questions, 2 fill-in-the-blanks cells and 2 written answers. 19 marks, about 35 to 45 minutes.

Series: H446 1.4.3 · Boolean algebra, part 9 of 11.

Shared by Coding PathwayVerified teacher

  • 12 cells
  • About 45 minutes
  • CC BY-SA 4.0
  • Shared 31 Aug 2026
  • Updated 3 Sept 2026

Preview

The whole resource, exactly as a class sees it. Answers and marking are held back.

D-type flip-flops

Combinational circuits such as adders calculate outputs from current inputs. A D-type flip-flop adds state: it can store one bit over time.

You should already know: Boolean values and the purpose of a clock signal in a processor.

Q follows D only at the active clock edge

D-type flip-flop timingClockDQrising edge: Q copies D = 0rising edge: Q copies D = 1

A D-type flip-flop has data input D, clock input, stored output Q, and often inverse output ¬Q. In the OCR-level model, Q copies D at a rising clock edge. Between rising edges, Q holds its previous value even if D changes.

This makes one flip-flop a one-bit memory element. Groups of them can form registers and buffers whose updates are synchronised by a shared clock.

Multiple choice1 mark

D changes from 0 to 1 halfway between two rising clock edges. What happens to Q immediately?

  • AQ changes to 1 immediately
  • BQ becomes undefined
  • CQ always changes to 0
  • DQ holds its previous value until the next rising edge
Fill in the blanks4 marks
Use the rule ‘sample D on ↑; otherwise hold Q’. The initial Q is 0.
EventDQ after event
D changes, no rising edge1event1 Q
Rising edge1event2 Q
D changes, no rising edge0event3 Q
Rising edge0event4 Q
Multiple choice1 mark

After a rising edge captures D=1, D changes 1→0→1 before the next rising edge. What is Q during those two changes?

  • AIt remains 1
  • BIt follows both changes
  • CIt remains 0
  • DIt alternates independently of D
Written answer4 marks

Explain how D-type flip-flops can be used to store a four-bit value in a register.

Link four one-bit elements, a shared clock and holding state between edges.

Students type their answer here.

Multiple choice1 mark

Which detail is explicitly outside the required OCR knowledge for D-type flip-flops?

  • AThat one flip-flop stores one bit
  • BThe complete arrangement of gates inside the flip-flop
  • CThat a clock pulse triggers a state change
  • DThat Q can hold a value

Keep the abstraction at the right level

Electronics texts distinguish latches and several types of edge-triggered flip-flop. For H446, focus on purpose, one-bit storage, D and Q, the clock and the rising-edge/hold behaviour. Do not spend revision time memorising a NAND-gate implementation.

Written answer4 marks

Compare a full adder and a D-type flip-flop as logic circuits.

Use the terms combinational, state, current inputs and stored value.

Students type their answer here.

Closed-book checkpoint

Retrieve the timing rule and scope from memory.

Fill in the blanks4 marks
The data input is labelled entry 1 and the stored output is entry 2. At a rising edge, the output entry 3 the data input. Between active edges, the output is entry 4.

Review your responses

Check every response against its command word and the supplied constraints. Strengthen unsupported answers with accurate method, mechanism, state or contextual consequence before submitting.