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OCR H446 1.4.3 Half and full adders

Part 8 of 11 · H446 1.4.3 · Boolean algebra

Adders are where Boolean algebra turns into arithmetic, and OCR H446 1.4.3 asks students to construct a full adder from correctly connected stages rather than recall a picture of one. This worksheet separates the jobs of the Sum and Carry outputs, then wires two half-adder stages together with the carry path made explicit.

Students will:

  • state the Sum and Carry outputs of a half adder for each pair of input bits
  • describe the differences between a half adder and a full adder
  • follow a carry-in through two XOR, two AND and one OR gate
  • work out full-adder outputs for given inputs including an incoming carry
  • draw and label a complete full-adder circuit

Inside: 5 explanation cells, 2 multiple-choice questions, 3 fill-in-the-blanks cells and 2 written answers. 21 marks, about 45 to 55 minutes.

Series: H446 1.4.3 · Boolean algebra, part 8 of 11.

Shared by Coding PathwayVerified teacher

  • 12 cells
  • About 45 minutes
  • CC BY-SA 4.0
  • Shared 31 Aug 2026
  • Updated 3 Sept 2026

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The whole resource, exactly as a class sees it. Answers and marking are held back.

Half and full adders

Adder circuits perform binary addition. A half adder combines two input bits. A full adder also accepts the carry arriving from the previous bit position.

You should already know: XOR, AND and OR truth conditions, and one-bit binary addition.

Worked model: two outputs have different jobs

Half-adder and full-adder signal rolesHalf adderFull adderABSum = A ⊕ BCarry = A ∧ BABCarry inSumCarry outXOR → SumAND → Carryadds three bitstwo half-adder stagesplus OR for carries

For a half adder, Sum = A ⊕ B and Carry = A ∧ B. The XOR output is the bit written in the current column; the AND output is carried into the next column.

A full adder has A, B and Carry in as inputs. It produces Sum and Carry out. A common construction uses two XOR gates, two AND gates and one OR gate.

Fill in the blanks4 marks
Complete the half-adder truth table.
ABSumCarry out
00row1 sumrow1 carry
01row2 sumrow2 carry
10row3 sumrow3 carry
11row4 sumrow4 carry
Multiple choice1 mark

Why does a half adder output Sum=0 and Carry=1 for A=1 and B=1?

  • AXOR is true when both inputs are true
  • B1 + 1 in binary is 10
  • CThe carry output is always 1
  • DA half adder has a hidden carry-in input
Written answer2 marks

Describe two differences between a half adder and a full adder.

Refer to inputs and how the circuit is used in multi-bit addition.

Students type their answer here.

Build a full adder from two half-adder stages

  1. First XOR: X = A ⊕ B.
  2. Second XOR: Sum = X ⊕ CarryIn.
  3. First AND: C1 = A ∧ B.
  4. Second AND: C2 = X ∧ CarryIn.
  5. OR: CarryOut = C1 ∨ C2.

Do not feed the first AND output into the second AND. The second AND must receive X and CarryIn, and both partial-carry signals must reach the final OR.

Fill in the blanks5 marks
For A=1, B=0 and CarryIn=1: X=entry 1, Sum=entry 2, C1=entry 3, C2=entry 4, CarryOut=entry 5.
Multiple choice1 mark

A full adder receives A=1, B=1 and CarryIn=1. What are Sum and CarryOut?

  • A0 and 0
  • B0 and 1
  • C1 and 1
  • D1 and 0
Written answer4 marks

On paper, draw and label a full-adder circuit using two XOR, two AND and one OR gate. Show A, B, CarryIn, Sum and CarryOut.

Follow the five-stage model above.

Students type their answer here.

Closed-book checkpoint

Complete the signal roles from memory. No answer bank is provided.

Fill in the blanks4 marks
In a half adder, XOR produces the entry 1 bit and AND produces the entry 2 bit. A full adder has a third input called entry 3. The two candidate carry signals are combined by an entry 4 gate.

Review your responses

Check every response against its command word and the supplied constraints. Strengthen unsupported answers with accurate method, mechanism, state or contextual consequence before submitting.