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1CP2-P-3.2 CPU components registers and buses
Part 2 of 7 · 1CP2-P-3 · Architecture and storage
The component worksheet, mapping the CPU and the three buses onto the work each one does.
Students will:
- distinguish the control unit from the ALU
- describe what registers hold while an instruction is processed
- distinguish the address bus from the data bus during a read
- match a transfer to the bus that carries it
- describe one complete memory read using all three buses
Inside: 5 explanation cells, 4 multiple-choice questions, 2 fill-in-the-blanks cells and 4 written answers. 20 marks, about 45 minutes.
Series: 1CP2-P-3 · Architecture and storage, part 2 of 7.
Shared by Coding PathwayVerified teacher
- 15 cells
- About 45 minutes
- CC BY-SA 4.0
- Shared 17 Aug 2026
Preview
The whole resource, exactly as a class sees it. Answers and marking are held back.
CPU components, registers and buses
The CPU coordinates and processes instructions. Main memory supplies the active instructions and data. Buses carry addresses, data and control signals between components.
Pearson expects you to understand what registers do in general; you do not need to memorise the names or jobs of individual registers.
1. Map the system
The control unit (CU) coordinates instruction processing and sends control signals. The arithmetic logic unit (ALU) performs arithmetic and logical operations. Registers are small, fast memory locations inside the CPU that temporarily hold data, instructions or intermediate results. The clock supplies regular timing pulses that coordinate operations.
- ALU
- address bus
- control unit
- registers
- RAM
Which statement accurately describes CPU registers?
- AThey permanently store all user files.
- BThey are small, fast locations for temporary values and intermediate results.
- CThey connect the computer to the internet.
- DThey provide every address in secondary storage.
Distinguish the role of the control unit from the role of the ALU.
State what each component contributes to instruction processing.
Students type their answer here.
2. Bus roles and directions
- The address bus carries the address of the location to access. It is unidirectional: from the CPU towards memory or a device.
- The data bus carries instructions and data. It is bidirectional because values can be read into the CPU or written away from it.
- The control bus carries commands and status signals, such as read and write. Signals can travel in both directions.
An address identifies where. Data is what is transferred. A control signal says what action should happen.
- address
- control
- data
- register
- storage
Which bus carries the contents of a fetched instruction from memory towards the CPU?
- AAddress bus
- BControl bus
- CData bus
- DClock bus
Distinguish the address bus from the data bus during a memory read.
State what each carries and its direction.
Students type their answer here.
3. Model one memory read
- The CPU places the required location on the address bus.
- The control unit sends a read signal along the control bus.
- Main memory places the contents of that location on the data bus.
- A CPU register temporarily holds the returned instruction or data.
The three buses cooperate, but each carries a different kind of information.
Describe the role of the control unit and all three buses when an instruction is fetched from memory.
Write a linked sequence rather than four unrelated definitions.
Students type their answer here.
Which component would carry out the comparison in an instruction such as score > 10?
- AALU
- BRegister
- CAddress bus
- DSecondary storage
Explain why registers are useful while an instruction is being processed.
Link their location and speed to temporary working values.
Students type their answer here.
Which transfer is accurately matched to its bus?
- AAddress bus: fetched instruction contents
- BControl bus: permanent program file
- CData bus: value being written to memory
- DClock: address of a RAM location
Route forward
You can identify CPU components and explain each transfer route without relying on named-register detail. Next you will assemble them into the ordered fetch-decode-execute cycle.