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1CP2-P-3.7 Architecture and storage checkpoint
Part 7 of 7 · 1CP2-P-3 · Architecture and storage
The checkpoint for the whole series, sampling the stored-program concept, the cycle, addressing and storage selection.
Students will:
- identify the feature central to the stored-program concept
- describe the fetch-decode-execute cycle including registers and buses
- explain a clock-speed performance claim precisely
- calculate addressable locations and the resulting capacity
- give a linked storage justification rather than a vague claim
Inside: 7 explanation cells, 3 multiple-choice questions, 1 fill-in-the-blanks cell and 5 written answers. 20 marks, about 45 minutes.
Series: 1CP2-P-3 · Architecture and storage, part 7 of 7.
Shared by Coding PathwayVerified teacher
- 16 cells
- About 45 minutes
- CC BY-SA 4.0
- Shared 17 Aug 2026
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Architecture and storage checkpoint
This strand-specific checkpoint retrieves the stored-program concept, CPU components, buses, the fetch-decode-execute cycle, RAM and clock speed, address capacity and secondary storage.
No new content is introduced. Use precise component names and link each explanation to a movement, effect or scenario requirement.
1. Rapid retrieval
Remember the relationships: shared RAM holds active instructions and data; registers temporarily hold working values; the address bus identifies locations; the data bus carries contents; the control bus carries coordinating signals; the CU decodes; the ALU calculates; secondary storage keeps data without power.
- ALU
- RAM
- address bus
- registers
- secondary storage
Which feature is central to the von Neumann stored-program concept?
- AInstructions and data share main memory.
- BEvery program has a separate CPU.
- COnly instructions have binary addresses.
- DSecondary storage performs all execution.
2. Reconstruct the cycle
A complete description should follow the instruction, not merely list component definitions. Identify its location, use the address and control buses to request it, return it on the data bus into a register, then explain decoding and execution.
Describe the fetch-decode-execute cycle, including the roles of registers, buses, the control unit and the ALU where appropriate.
Write a connected sequence from the next instruction location to the completed operation.
Students type their answer here.
3. Clock and memory reasoning
The clock synchronises CPU operations using regular pulses. Clock speed is measured in hertz, meaning cycles per second. RAM is volatile main memory; secondary storage is non-volatile and keeps saved programs and data.
Explain how a higher clock speed can improve the performance of an otherwise comparable CPU.
Link frequency to processing work rather than saying only 'faster'.
Students type their answer here.
4. Address calculation
Use 2ⁿ locations for an n-bit address bus. State the expression before the result. Remember that a location count becomes bytes only if bytes per location are known.
A system has a 14-bit address bus. Calculate its number of addressable locations. If each location stores 2 bytes, calculate the total capacity in bytes.
Calculate 2 to the power 14, then multiply by 2.
Students type their answer here.
During fetch, which pairing is accurate?
- AAddress bus: instruction contents; data bus: location
- BAddress bus: location; data bus: instruction contents
- CControl bus: permanent file; data bus: clock pulse
- DData bus: address only; ALU: read signal
5. Scenario selection
A field recorder needs removable storage that is small, resistant to movement and quick enough to save frequent recordings. A justified response names the technology and connects properties to these particular needs.
Select a suitable storage technology for the field recorder and justify your choice using two scenario requirements.
Use technology, property and consequence links.
Students type their answer here.
Correct both errors in this claim: 'RAM is non-volatile secondary storage, and a 6-bit address bus selects 12 locations.'
Give the corrected role/property and calculation.
Students type their answer here.
Which answer is a linked storage justification rather than a vague claim?
- AUse solid state because it is best.
- BUse optical because discs exist.
- CUse magnetic tape because high archive capacity at low cost suits rarely accessed backups.
- DUse RAM because it keeps files without power.
Route forward
This checkpoint closes 1CP2-P-3. Later principles series retrieve these foundations when studying embedded systems, operating systems and other hardware contexts.