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1CP2-P-3.3 The fetch decode execute cycle

Part 3 of 7 · 1CP2-P-3 · Architecture and storage

The cycle worksheet, taken one stage at a time and then described end to end.

Students will:

  • name the three recurring stages and state what each produces
  • model the fetch stage using the registers and buses involved
  • distinguish execution from decoding
  • describe the whole cycle from locating an instruction to carrying it out
  • explain why the cycle repeats while a program runs

Inside: 6 explanation cells, 3 multiple-choice questions, 2 fill-in-the-blanks cells and 3 written answers. 18 marks, about 45 minutes.

Series: 1CP2-P-3 · Architecture and storage, part 3 of 7.

Shared by Coding PathwayVerified teacher

  • 14 cells
  • About 45 minutes
  • CC BY-SA 4.0
  • Shared 17 Aug 2026

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The whole resource, exactly as a class sees it. Answers and marking are held back.

The fetch-decode-execute cycle

A stored program becomes useful only when its instructions are processed. The CPU repeatedly fetches the next instruction, decodes what it means and executes the required operation.

High-quality exam explanations name both the movement and the component responsible.

1. Three recurring stages

Fetch decode execute cycleFETCHnext instructionRAM → registersDECODEcontrol unit interpretsoperation and dataEXECUTEoperation is carried outresult is storedrepeat for the next instruction

Fetch moves an instruction from RAM into CPU registers. Decode makes the control unit interpret the operation and any required data. Execute carries out that operation using the appropriate component, such as the ALU, memory or an input/output device.

Fill in the blanks3 marks
During gap 1, the instruction is moved from memory. During gap 2, the control unit interprets it. During gap 3, the operation is carried out.
  • decode
  • execute
  • fetch
  • store

2. Model the fetch stage

A precise GCSE-level sequence is:

  1. The CPU identifies the address of the next instruction.
  2. It sends that address to RAM on the address bus.
  3. The control unit sends a memory-read signal on the control bus.
  4. RAM sends the instruction back on the data bus.
  5. A CPU register temporarily holds the fetched instruction.

You need to explain the movement and bus roles, but Pearson does not require the names of individual registers.

Fill in the blanks3 marks
During fetch, the instruction address travels on the gap 1 bus, a read signal travels on the gap 2 bus, and the instruction returns on the gap 3 bus.
  • address
  • control
  • data
  • register
  • storage
Multiple choice1 mark

What is the result of the fetch stage?

  • AThe next instruction has been moved from RAM into a CPU register.
  • BEvery file has been copied to secondary storage.
  • CThe ALU has always completed a calculation.
  • DThe program has permanently stopped.

3. Decode and execute

The control unit decodes the fetched instruction: it interprets the operation and what data is needed, then sends the control signals required to carry it out.

During execute, the requested operation happens. The ALU may calculate or compare; data may move between a register and memory; or an input/output operation may occur. A result may be held in a register or written to memory.

Multiple choice1 mark

Which is an example of execution rather than decoding?

  • AThe control unit identifies that an instruction means ADD.
  • BThe ALU adds two values and stores the result.
  • CRAM supplies the fetched instruction.
  • DThe address bus identifies the instruction location.
Written answer5 marks

Describe the fetch-decode-execute cycle from locating the next instruction to carrying out its operation.

Aim for a connected sequence using registers, buses and the control unit.

Students type their answer here.

4. The cycle repeats

After execution, the CPU fetches the next required instruction and repeats the three stages. Programs normally follow their instruction sequence, while selection and repetition can change which instruction is required next.

The important examination idea is still the same ordered process: fetch → decode → execute → repeat.

Written answer2 marks

Explain why the fetch-decode-execute cycle must repeat while a program is running.

Link a program containing many instructions to processing the next required instruction.

Students type their answer here.

Multiple choice1 mark

A student says the address bus carries the fetched instruction into a CPU register. What is the correction?

  • AThe control bus carries the instruction.
  • BThe ALU carries the instruction.
  • CThe data bus carries the instruction; the address bus carries its location.
  • DThe clock carries both address and instruction.
Written answer2 marks

An instruction requires two values to be compared. Describe what the control unit and ALU each do during decode and execute.

Keep interpretation and operation separate.

Students type their answer here.

Route forward

You can now explain the cycle as movement, interpretation and action. Next you will connect active RAM, persistent storage and the clock that synchronises processor operations.