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1CP2-P-3.5 Address buses and addressable memory
Part 5 of 7 · 1CP2-P-3 · Architecture and storage
The addressing worksheet, turning a bus width into a count of locations and then into a capacity.
Students will:
- calculate the locations an address bus of a given width can select
- show the expression as well as the result
- state what else is needed to convert locations into bytes
- distinguish the effect of address-bus width from data-bus width
- explain why one extra address bit doubles the locations
Inside: 6 explanation cells, 3 multiple-choice questions, 2 fill-in-the-blanks cells and 4 written answers. 18 marks, about 45 minutes.
Series: 1CP2-P-3 · Architecture and storage, part 5 of 7.
Shared by Coding PathwayVerified teacher
- 15 cells
- About 45 minutes
- CC BY-SA 4.0
- Shared 17 Aug 2026
Preview
The whole resource, exactly as a class sees it. Answers and marking are held back.
Address buses and addressable memory
Every main-memory location needs a unique binary address. The width of the address bus is the number of address bits that can be carried at once. It limits how many distinct locations the CPU can select.
This is a binary-states calculation: n bits can form 2ⁿ different patterns.
1. Turn bits into locations
A 3-bit address bus carries 000 through 111, giving 2³ = 8 unique addresses. A 4-bit address bus gives 2⁴ = 16; 8 bits gives 2⁸ = 256.
Each additional address line doubles the address count because every old pattern can occur with a leading 0 or a leading 1.
n can represent gap 1 unique addresses. Increasing the width by one gap 2 the location count. The address bus identifies a gap 3, not the contents stored there.- 2 × n
- 2ⁿ
- doubles
- location
- value
How many unique memory locations can a 4-bit address bus select?
- A4
- B8
- C16
- D32
2. Show the expression
For an exam calculation, write the power before the result:
10 address bits → 2¹⁰ = 1024 locations
Do not calculate 10 × 2. The bits are independent binary choices, so the number of combinations grows exponentially.
Calculate the number of addressable locations for a 12-bit address bus. Show the expression and result.
Use 2 to the power of the bus width.
Students type their answer here.
| Address width | Expression | Locations |
|---|---|---|
| 5 bits | 2⁵ | gap 1 |
| 8 bits | gap 2 | 256 |
| gap 3 bits | 2¹⁶ | 65,536 |
- 16
- 2⁸
- 32
- 256
- 8
3. Locations are not automatically bytes
The address-width calculation gives a number of locations. To turn that into a memory capacity, the amount stored at each address must also be known.
If a system is byte-addressable, each location stores one byte, so 16 address bits can select 65,536 bytes. If each location stores two bytes, the same number of addresses represents twice that data capacity. State assumptions rather than silently treating every location as one byte.
Which information is needed in addition to 10 address bits to calculate total capacity in bytes?
- AThe colour of the motherboard
- BThe number of bytes stored per addressable location
- CThe number of clock cycles per second
- DThe optical-disc speed
A system has a 10-bit address bus and stores 2 bytes at each address. Calculate its addressable capacity in bytes.
First calculate locations, then multiply by bytes per location.
Students type their answer here.
4. Address bus versus data bus
A wider address bus can identify more locations. A wider data bus can carry more data bits in one transfer. These are separate properties. Changing data-bus width does not create extra address patterns.
Distinguish the effect of increasing address-bus width from increasing data-bus width.
Use locations for one and bits per transfer for the other.
Students type their answer here.
Explain why a 9-bit address bus can select twice as many locations as an 8-bit address bus.
Describe the new leading-bit choice.
Students type their answer here.
Which expression gives the locations addressable by a 20-bit address bus?
- A20²
- B20 × 2
- C2²⁰
- D2 + 20
Route forward
You can calculate addressable locations and state capacity assumptions. Next you will compare persistent storage technologies and calculate storage requirements for a stated purpose.