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OCR H446 1.1.1 Decode, execute and branching

Part 5 of 12 · H446 1.1.1 · Structure and function of the processor

OCR H446 1.1.1: Decode, execute and branching. Students learn to distinguish decode from execute and predict how arithmetic, comparison and branch instructions change processor state.

Students will:

  • follow decode and execute stages
  • track the effect of instructions on processor state
  • explain how branching changes instruction flow

Inside: 5 explanation cells, 1 multiple-choice question, 2 fill-in-the-blanks cells and 2 written answers. 16 marks, about 20 to 30 minutes.

Series: H446 1.1.1 · Structure and function of the processor, part 5 of 12.

Shared by Coding PathwayVerified teacher

  • 10 cells
  • About 30 minutes
  • CC BY-SA 4.0
  • Shared 31 Aug 2026
  • Updated 3 Sept 2026

Preview

The whole resource, exactly as a class sees it. Answers and marking are held back.

Decode, execute and branching

After fetching an instruction, the processor must interpret it and carry out the required operation. The execute stage is not one fixed transfer: it changes according to the instruction.

By the end, you will be able to

  • distinguish decode from execute;
  • predict register effects for arithmetic, store and branch instructions;
  • explain how a branch changes the next fetch.

You will be given each low-level instruction's meaning. Remembering an assembly mnemonic is not the purpose of this sheet.

From binary pattern to action

The instruction in the Current Instruction Register (CIR) contains an opcode, which identifies the operation, and may contain an operand, such as data or an address used by that operation. During decode, the Control Unit (CU) interprets these parts and prepares the required control signals and data paths. During execute, the action depends on the opcode:

Instruction typeModelled execute effect
arithmeticthe Arithmetic Logic Unit operates and the Accumulator holds the result
storethe target address is held in the Memory Address Register, the value passes through the Memory Data Register, and a write signal is sent
branchthe Program Counter receives the target address if the condition is satisfied
How a conditional branch selects the address for the next fetch after fetchPC holds next sequentialaddress decodeCU interprets operation,condition and target executetest branch condition condition falsecondition true PC remains sequentialnext fetch follows normal order PC receives targetnext fetch jumps to target The branch changes the PC during execute; the CIR still holds the current instruction.

A branch changes control flow by changing the Program Counter (PC). The PC does not merely count completed instructions.

Worked conditional branch

A supplied instruction means branch to address 480 if the last result was zero. After fetch, the PC holds the next sequential address, 206.

  1. Decode identifies the branch operation, the zero condition and target 480.
  2. During execute, the relevant zero condition is tested.
  3. If it is true, PC becomes 480. If it is false, PC remains 206.
  4. The next fetch begins at whichever address the PC now holds.

This models the processor effect without requiring mnemonic recall.

Multiple choice1 mark

When is a taken branch target normally written to the PC?

  • ABefore the branch instruction is fetched
  • BDuring execution of the branch instruction
  • CWhenever the MDR contains any data
  • DOnly after the program ends
Fill in the blanks3 marks
The gap 1 interprets the instruction in CIR. An arithmetic instruction is then performed by the gap 2, while a taken branch changes the gap 3.
  • control unit
  • ALU
  • PC
  • MDR
Written answer4 marks

A supplied instruction means ‘add the value at address 90 to the Accumulator’. Distinguish its decode and execute stages.

State what is interpreted first, then what action and register result follow.

Students type their answer here.

Written answer4 marks

A supplied instruction means ‘branch to address 600 if the last result was zero’. After fetch, PC = 241. Explain the final PC value if the zero condition is (a) true and (b) false.

Give both values and link each to branch execution.

Students type their answer here.

Checkpoint

Complete the cycle and instruction effects from memory. There is no answer bank.

Fill in the blanks4 marks
A supplied instruction means ‘store the current result at address 700’. During execute, the value begins in the checkpoint gap 1 and is copied through the checkpoint gap 2. The target address 700 is held in the checkpoint gap 3, and the CU sends a checkpoint gap 4.

Consolidate your understanding

Check that you can separate decoding from execution and predict both taken and not-taken branch states.