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OCR H446 1.1.1 Named registers and low-level instruction bridge

Part 2 of 12 · H446 1.1.1 · Structure and function of the processor

OCR H446 1.1.1: Named registers and low-level instruction bridge. Students learn to identify named CPU registers from their contents and track register state through simple low-level instructions.

Students will:

  • identify registers from the values they hold
  • track register state through low-level instructions
  • diagnose register contents in unfamiliar processor states

Inside: 6 explanation cells, 1 multiple-choice question, 2 fill-in-the-blanks cells and 2 written answers. 14 marks, about 20 to 30 minutes.

Series: H446 1.1.1 · Structure and function of the processor, part 2 of 12.

Shared by Coding PathwayVerified teacher

  • 11 cells
  • About 30 minutes
  • CC BY-SA 4.0
  • Shared 31 Aug 2026
  • Updated 3 Sept 2026

Preview

The whole resource, exactly as a class sees it. Answers and marking are held back.

Named registers and a low-level instruction bridge

Registers are tiny, fast stores inside the processor. OCR names five whose contents you must distinguish. This sheet gives each full name before using its abbreviation.

By the end, you will be able to

  • state what each named register holds;
  • follow one carefully modelled load, add and store journey;
  • avoid describing a register as if it actively moves or processes data.

Detailed assembly programming and addressing modes are taught later in H446 section 1.2.4. Here, low-level instructions only help us see how processor parts cooperate.

Five different jobs

Full names and contents of five processor registersProgram CounterPCaddress of the nextinstructionMemory AddressRegister (MAR)address currentlybeing accessedMemory DataRegister (MDR)data or instructionbeing transferredCurrent InstructionRegister (CIR)current instructionbeing decodedAccumulatorACCworking value orALU resultRead the noun after “holds”PC and MAR hold addresses. MDR and ACC can hold values.CIR holds the current instruction.A register holds a value; control signals and buses cause transfers.

  • The Program Counter (PC) holds the address of the next instruction.
  • The Memory Address Register (MAR) holds the address currently being accessed.
  • The Memory Data Register (MDR) holds data or an instruction being transferred to or from memory.
  • The Current Instruction Register (CIR) holds the current instruction while it is decoded and executed.
  • The Accumulator (ACC) holds a working value, operand or Arithmetic Logic Unit result.

The PC is not simply a count of completed instructions. A branch can replace its next address.

Read a low-level instruction

A machine instruction is stored as binary. It contains an opcode, which identifies the operation, and usually an operand, which gives data or a location used by the operation. Assembly language uses readable mnemonics for these patterns. For this model only: LDA 42 means load the value at address 42, ADD 43 means add the value at address 43, and STA 44 means store the result at address 44. You are not being asked to write an assembly program here.

Worked register journey

Memory locations 42 and 43 contain 18 and 7.

  1. LDA 42: 42 is held in MAR, the value 18 returns through MDR, and 18 is copied to ACC.
  2. ADD 43: 43 is held in MAR, 7 returns through MDR, and the ALU produces 25 in ACC.
  3. STA 44: 44 is held in MAR, while 25 passes through MDR to memory.

Focus on what each register holds. The buses and control signals cause the transfers.

Multiple choice1 mark

Immediately before the next instruction is fetched, what should the PC hold?

  • AThe current arithmetic result
  • BThe address of the next instruction
  • CThe current instruction itself
  • DThe number of instructions executed
Fill in the blanks4 marks
During a memory access, the gap 1 holds the address and the gap 2 holds the value being transferred. The instruction being decoded is held in the gap 3, while an ALU result may be held in the gap 4.
  • MAR
  • MDR
  • CIR
  • ACC
  • PC
Written answer3 marks

The supplied instruction LDA 80 means ‘load the value at memory address 80’. Location 80 contains 12. Explain the register changes when it executes.

Use address → MAR, memory value → MDR, then destination register. No other assembly knowledge is needed.

Students type their answer here.

Written answer2 marks

Explain one difference between the contents of the PC and CIR.

State what both registers hold; do not merely expand their names.

Students type their answer here.

Checkpoint

Diagnose four processor states. Each instruction meaning is supplied, so no mnemonic recall is needed. There is no answer bank.

Fill in the blanks4 marks
An input instruction places the entered value 6 in the checkpoint gap 1. After an addition, the ALU result 11 may also be held in the checkpoint gap 2. A zero-branch instruction can test the working value in the checkpoint gap 3, but a taken branch writes its target address to the checkpoint gap 4.

Consolidate your understanding

Check that each register is identified by what it holds and that every instruction-state change is explicit.