Processor pipelining

Without pipelining, parts of the Central Processing Unit (CPU) may wait while one instruction completes every stage. A pipeline overlaps stages of different instructions.

By the end, you will be able to

• explain overlap and throughput;
• distinguish pipelining from multiple cores;
• reason about stalls, branches and latency.

Different instructions, different stages

Imagine three people preparing letters: one folds, one puts each letter in an envelope and one seals it. They can work on different letters at the same time instead of waiting for one whole letter to finish. A processor pipeline applies the same idea to instruction stages.

Once the pipeline fills, one instruction may complete per clock cycle in this simplified model. This increases throughput, meaning instructions completed per unit time. It does not necessarily reduce the latency of one instruction. Dependencies, unequal stage times and branches can cause stalls; a wrong predicted branch may require fetched work to be discarded. Some processors also divide arithmetic into pipeline stages, but OCR's core requirement here is overlapping instruction processing.

Worked timing

Three instructions with three one-cycle stages take 9 stage-cycles sequentially. Ideal overlap completes them after 5 cycles: FDE for I1, then I2 begins one cycle later, then I3. Real savings can be smaller because a later instruction may need an earlier result. This is one core overlapping stages, not three cores running three programs.

Checkpoint

Complete the pipeline explanation from memory. There is no answer bank.

Consolidate your understanding

Check that you can explain stage overlap, throughput and disruption without confusing pipelining with multiple cores.