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OCR H446 1.1.1 Processor structure and function consolidation
Part 9 of 12 · H446 1.1.1 · Structure and function of the processor
OCR H446 1.1.1: Processor structure and function consolidation. This worksheet consolidates the complete processor row through interleaved retrieval, state tracing, causal explanation and architecture comparison.
Students will:
- retrieve the processor component and transfer model
- trace unfamiliar processor states
- combine performance explanations and architecture comparisons
Inside: 2 explanation cells, 1 multiple-choice question, 1 fill-in-the-blanks cell and 7 written answers. 40 marks, about 45 to 60 minutes.
Series: H446 1.1.1 · Structure and function of the processor, part 9 of 12.
Shared by Coding PathwayVerified teacher
- 11 cells
- About 45 minutes
- CC BY-SA 4.0
- Shared 31 Aug 2026
- Updated 3 Sept 2026
Preview
The whole resource, exactly as a class sees it. Answers and marking are held back.
Processor structure and function: consolidation
This sheet interleaves the complete 1.1.1 story. Work closed-book first, then repair answers using the explanation prompts.
Retrieval route
component → register → bus width and capacity → FDE sequence → performance mechanism → architecture comparison.
Which register holds the instruction currently being decoded?
- APC
- BCIR
- CMAR
- DACC
- PC
- MAR
- MDR
- CIR
- ACC
Describe the purpose of all three buses.
For each, state exactly what it carries.
Students type their answer here.
A system has a 12-bit address bus and word-addressable memory. Each word is 16 bits. Calculate the memory capacity in bytes and KiB.
Show the number of addresses, multiply by the bits stored at each address, then convert bits to bytes.
Students type their answer here.
Explain why a taken branch changes the PC rather than the CIR.
Contrast what each register holds and link to the next fetch.
Students type their answer here.
A processor is upgraded from four to eight cores, but a dependent single-threaded task barely improves. Explain why.
Use parallel work, dependencies and another possible bottleneck.
Students type their answer here.
Explain how pipelining can increase efficiency and why a branch can reduce the gain.
Separate normal overlap from disruption.
Students type their answer here.
Compare Von Neumann and Harvard architectures, then explain one supplied contemporary example: SIMD, MIMD or distributed computing.
Use matched comparisons, then explain the named example in accessible language.
Students type their answer here.
Evaluate replacing a shared-memory processor with a Harvard-style processor in a low-cost device that repeatedly processes a fixed sensor stream.
Develop access benefit, cost/complexity limitation and a conditional conclusion.
Students type their answer here.
Review your understanding
Use the evidence in your answers to identify what to strengthen. Check that you can:
- distinguish CU and ALU actions from values held in registers;
- track ACC, PC, MAR, MDR and CIR through a processor state;
- name what each bus carries and separate word, address and data-bus widths;
- calculate capacity from the number and size of addressable locations;
- reconstruct the fetch sequence and separate decode, execute and branch effects;
- explain clock, core and cache effects and state when each benefit may be limited;
- explain pipeline overlap and branch disruption;
- compare the same architecture feature on both sides.
Rework any response that relies on an unsupported label, missing unit or generic claim.