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OCR H446 1.1.1 Word size, bus width and addressable memory

Part 12 of 12 · H446 1.1.1 · Structure and function of the processor

OCR H446 1.1.1: Word size, bus width and addressable memory. Students learn to distinguish word size, address-bus width and data-bus width, then calculate addressable capacity; word size has been credited in OCR sample assessment marking, but it is not named as a standalone specification or content-guide point.

Students will:

  • distinguish word size, address-bus width and data-bus width
  • calculate addressable memory capacity
  • apply the model to unfamiliar values and diagnose incorrect claims

Inside: 5 explanation cells, 1 multiple-choice question, 2 fill-in-the-blanks cells and 3 written answers. 21 marks, about 25 to 35 minutes.

Series: H446 1.1.1 · Structure and function of the processor, part 12 of 12.

Shared by Coding PathwayVerified teacher

  • 11 cells
  • About 30 minutes
  • CC BY-SA 4.0
  • Shared 3 Sept 2026

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Word size, bus width and addressable memory

Processor descriptions often give several measurements in bits. These measurements are connected, but they do not describe the same thing. First decide what each number measures. Then choose the numbers needed for the calculation.

By the end, you will be able to

  • explain word size, address-bus width and data-bus width;
  • calculate the number of addressable locations;
  • calculate memory capacity when the size of each location is stated;
  • explain why machine code written for one processor may not run on another.

Start with what each number tells you

From address-bus width and addressable unit to memory capacity Keep the three widths separate address bus: a bits wide selects 2ᵃ locations It does not say how largeeach location is. data bus: d bits wide moves d bits per transfer Transfer width alone does notgive memory capacity. word size: w bits bits handled as one unit It may affect an operation, butis not the address width. then identify what each address stores capacity = number of locations × size of each location 2ᵃ × bits per addressable location Example: 10-bit address bus, byte-addressable memory 2¹⁰ addresses × 1 byte = 1024 bytes = 1 KiB
  • Word size is the number of bits that a processor handles as one unit. For example, a processor with a 16-bit word size can handle a 16-bit pattern as one unit. The exact operation depends on its instruction set. An instruction set is the collection of machine-code instructions that a processor can decode and execute.
  • Address-bus width tells you how many bits are available for an address. An address bus that is a bits wide can represent 2^a different addresses.
  • Data-bus width tells you how many bits can move in one transfer. A 16-bit data bus can transfer 16 bits, or 2 bytes, at a time.
  • An addressable location is one numbered place in memory. You must know what each location stores before calculating capacity. In byte-addressable memory, each address identifies one byte. In word-addressable memory, each address identifies one word.

Do the widths have to match?

In a simplified example, the word size, register width and data-bus width may be the same. Do not assume that they are equal unless the question tells you. The address-bus width has a different purpose: it determines the number of available addresses.

When might a wider word or data bus help?

Suppose a system needs to transfer a 16-bit value. An 8-bit data bus may need two transfers. A 16-bit data bus may transfer the value in one. A wider word can also allow some larger bit patterns to be handled in one operation. These changes may help a suitable task, but they do not prove that the whole processor will always be faster. Clock speed, cache, cores, processor design and the workload also matter.

Use the same capacity method every time

  1. Use the address-bus width to count the addresses.
  2. State what one address identifies.
  3. Multiply the number of addresses by the size of one addressable location.
  4. Convert the answer into the requested unit.

Byte-addressable memory

A system has a 10-bit address bus. Each address identifies one byte.

  1. Addresses: 2^10 = 1024.
  2. Capacity: 1024 × 1 byte = 1024 bytes = 1 KiB.

Word-addressable memory

A system has a 12-bit address bus. Each address identifies one 16-bit word.

  1. Addresses: 2^12 = 4096.
  2. Capacity: 4096 × 16 = 65,536 bits.
  3. In bytes: 65,536 ÷ 8 = 8192 bytes = 8 KiB.

KiB means 1024 bytes. Keep a unit beside every value so that addresses, bits and bytes do not become mixed together.

Multiple choice1 mark

A processor has a 16-bit data bus. What does this information tell you?

  • AIt has exactly 65,536 memory locations
  • BEvery memory address stores 16 bytes
  • CIts address bus must also be 16 bits wide
  • DIt can transfer 16 bits, or 2 bytes, at one time
Fill in the blanks3 marks
An address bus that is gap 1 bits wide can select 2^a locations. Total capacity is the number of locations multiplied by the size of each gap 2. Divide a capacity in bits by gap 3 to convert it to bytes.
  • a
  • addressable unit
  • 8
  • data bus
Written answer5 marks

A processor has a 16-bit word size and a 16-bit data bus. Its memory has a 14-bit address bus. Each address identifies a 2-byte location. Calculate the total memory capacity in bytes and KiB.

Not every width is needed. First choose the facts that give the number and size of the addressable locations. Show your working and include units.

Students type their answer here.

Written answer4 marks

A processor description gives only one fact: it has a 16-bit word size. A student says, ‘It must address exactly 65,536 bytes of memory.’ Explain why the student cannot reach that conclusion.

Explain what word size tells you. Then state the two pieces of information needed to calculate memory capacity.

Students type their answer here.

Written answer4 marks

An old control program is stored as machine code for Processor A. Processor B uses a different instruction set and a different word size. Explain why Processor B may not run the program correctly.

Explain how each processor interprets binary instructions. Word size can contribute, but it does not decide compatibility by itself.

Students type their answer here.

Checkpoint

Complete each gap from memory. No answer bank is provided.

Fill in the blanks4 marks
An 18-bit address bus provides checkpoint gap 1 different addresses. Each address stores one byte. Therefore, the memory capacity is checkpoint gap 2 bytes, or checkpoint gap 3 KiB. The bus width that tells you how many bits move in one transfer is the checkpoint gap 4 width.

Review the method

Before finishing a calculation, check that you have:

  • identified what each width measures;
  • stated what one address stores;
  • kept addresses, bits, bytes and KiB clearly labelled.

When explaining compatibility, discuss the instruction set as well as word or bus widths. Word size alone does not decide whether machine code will run.