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OCR H446 1.1.1 Processor pipeline state and schedule clinic

Part 11 of 12 · H446 1.1.1 · Structure and function of the processor

OCR H446 1.1.1: Processor pipeline state and schedule clinic. Students develop directly examined pipeline-schedule skills through construction, rule checks and diagnosis of dependency and branch disruption.

Students will:

  • construct an ideal pipeline schedule
  • diagnose dependency and branch disruption
  • evaluate claims about pipeline performance

Inside: 5 explanation cells, 2 fill-in-the-blanks cells, 1 multiple-choice question and 3 written answers. 26 marks, about 25 to 35 minutes.

Series: H446 1.1.1 · Structure and function of the processor, part 11 of 12.

Shared by Coding PathwayVerified teacher

  • 11 cells
  • About 30 minutes
  • CC BY-SA 4.0
  • Shared 31 Aug 2026
  • Updated 3 Sept 2026

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Processor pipeline state and schedule clinic

By the end, you will be able to

  • construct an ideal fetch–decode–execute schedule;
  • check the rules that must always be true for stage order and overlap;
  • diagnose dependency and branch disruption;
  • judge a performance claim without confusing pipelining with extra cores.

Reactivate: pipelining places different instructions in different stages at the same time. It can increase throughput, the number of completed instructions per unit time, without necessarily reducing the latency of one instruction.

Build the diagonal, then check it

Constructing an ideal four-instruction pipeline schedulecycle 1cycle 2cycle 3cycle 4cycle 5cycle 6instruction Ainstruction Binstruction Cinstruction DfetchdecodeexecutefetchdecodeexecutefetchdecodeexecutefetchdecodeexecuteEach instruction moves right one stage; each new instruction begins one cycle later.Ideal check for this equal-stage model: 4 instructions + 3 stages − 1 = 6 cycles.

This is a simplified model: fetch, decode and execute each last one cycle, and there are no stalls. Construct one instruction row at a time. Each instruction keeps the order fetch → decode → execute and moves one stage to the right each cycle. Start the next instruction one cycle later, producing the diagonal.

For this ideal equal-stage model, instructions + stages − 1 checks the final cycle. It is a checking relationship, not a formula to quote when a schedule contains a stall. Four instructions and three stages finish in cycle 6. Sequential processing would use 12 stage-cycles. The pipeline improves completion rate after filling; instruction A still uses three stages.

Fill in the blanks6 marks
Complete the missing stages in this ideal three-instruction schedule. Cycle 1: I1 fetch. Cycle 2: I1 gap 1, I2 gap 2. Cycle 3: I1 execute, I2 gap 3, I3 gap 4. Cycle 4: I2 execute, I3 gap 5. Cycle 5: I3 gap 6.
  • fetch
  • decode
  • execute
Multiple choice1 mark

A proposed cycle contains L1 execute, L2 decode and L3 execute. Earlier cycles show that L3 has not yet been fetched or decoded. What is the precise fault?

  • AThe processor needs three cores
  • BL1 must return to fetch
  • CEvery cycle may contain only one stage
  • DL3 executes before completing its earlier stages

When the ideal diagonal breaks

A schedule is valid only under its stated rules. For the next tasks use these supplied rules:

  • dependency rule: instruction R2 needs the result of R1 and cannot begin decode until the cycle after R1 executes; waiting is shown as a stall or bubble;
  • branch rule: a branch is resolved during execute; sequential instructions fetched before a taken branch is resolved may be wrong-path work and must be discarded before fetching restarts at the target.

Real processors can handle these situations in more complicated ways. At this level, explain which work is delayed or discarded and how that reduces the ideal throughput gain.

Written answer6 marks

Construct an ideal schedule for five independent instructions M1–M5 using one-cycle fetch, decode and execute stages. List the active stages in each cycle and state the final completion cycle.

You may use a table, diagram or cycle-by-cycle list. Check stage order, diagonal overlap and the ideal completion relationship.

Students type their answer here.

Written answer5 marks

In an ideal schedule R1 executes in cycle 3 while R2 would normally decode in cycle 3. Apply the supplied dependency rule to R2. Then explain what happens if R1 is instead a taken branch and the already-fetched R2 and R3 are on the wrong path.

Treat the dependency and branch as two separate disruptions. State a schedule/state change and its throughput consequence for each.

Students type their answer here.

Written answer4 marks

A designer claims: ‘Four instructions always finish in six cycles because this processor is pipelined.’ Evaluate the claim.

Separate the ideal model from the word always. Use at least two conditions or disruptions before concluding.

Students type their answer here.

Consolidate your understanding

Complete the ideal-model checks and disruption language from memory without an answer bank.

Fill in the blanks4 marks
Six independent instructions passing through three one-cycle stages finish ideally in cycle checkpoint gap 1, compared with checkpoint gap 2 stage-cycles sequentially. Pipelining primarily increases checkpoint gap 3; after a taken branch, wrong-path instructions may be checkpoint gap 4.

Review your schedule

Check that each instruction follows fetch → decode → execute, moves by no more than one stage per cycle and overlaps only with stages from other instructions. Rework any disruption explanation that does not identify the lost or delayed work.