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OCR H446 1.1.1 Fetch stage register and bus sequence

Part 4 of 12 · H446 1.1.1 · Structure and function of the processor

OCR H446 1.1.1: Fetch stage register and bus sequence. Students learn to reconstruct the fetch stage as an ordered sequence of register transfers, bus activity and control signals.

Students will:

  • reconstruct the fetch stage in order
  • connect register transfers to bus activity and control signals
  • apply the sequence to new register states

Inside: 5 explanation cells, 1 multiple-choice question, 2 fill-in-the-blanks cells and 2 written answers. 19 marks, about 25 to 35 minutes.

Series: H446 1.1.1 · Structure and function of the processor, part 4 of 12.

Shared by Coding PathwayVerified teacher

  • 10 cells
  • About 30 minutes
  • CC BY-SA 4.0
  • Shared 31 Aug 2026
  • Updated 3 Sept 2026

Preview

The whole resource, exactly as a class sees it. Answers and marking are held back.

The fetch stage: a precise transfer story

The fetch stage obtains the next instruction from memory. A complete description gives the events in order and uses the named registers and buses, rather than listing abbreviations without explaining their roles.

By the end, you will be able to

  • reconstruct the fetch sequence;
  • state the value held or carried at each step;
  • explain why the Program Counter changes.

Follow the address, then the instruction

Register and bus sequence during the fetch stage1 PC → MARnext address2 address buscarries address3 control buscarries read4 data busreturns contents5 MDRholds contents6 CIRholds instructionThe PC is incremented during fetchA later branch may replace that next address during execute.Register keyPC: Program Counter MAR: Memory Address Register MDR: Memory Data RegisterCIR: Current Instruction RegisterIn an exam answer, name the source, destination and what each bus carries.

A standard account is:

  1. The address in the Program Counter (PC) is copied to the Memory Address Register (MAR).
  2. The address bus carries that address to memory.
  3. The Control Unit sends a read signal on the control bus.
  4. The data bus returns the memory contents to the Memory Data Register (MDR).
  5. The instruction is copied to the Current Instruction Register (CIR).
  6. The PC is incremented so it normally identifies the following instruction.

Exact internal timing can vary, but these roles remain the same.

Worked state

Initially PC = 120 and memory location 120 contains instruction X. The instruction's meaning is irrelevant during fetch: the processor first has to obtain the whole binary pattern.

  • MAR receives 120.
  • The buses complete the memory read.
  • MDR, then CIR, holds instruction X.
  • PC becomes 121, ready for the following sequential fetch.

Instruction X is decoded and acted on only after the fetch stage.

Multiple choice1 mark

Which transfer begins the usual fetch description?

  • APC → MAR
  • BACC → ALU
  • CMDR → PC
  • DCIR → address bus
Fill in the blanks4 marks
The address in the gap 1 is copied to the gap 2. Memory contents return into the gap 3 and the instruction is copied to the gap 4.
  • PC
  • MAR
  • MDR
  • CIR
  • ACC
Written answer6 marks

Describe the fetch stage, including registers and buses.

Write an ordered chain. Use at least two named buses and four named registers.

Students type their answer here.

Written answer4 marks

PC = 350 and memory location 350 contains instruction Y. State the contents of MAR, MDR, CIR and PC immediately after the fetch.

Assume the sequential increment occurs during fetch. Instruction Y has not yet executed.

Students type their answer here.

Checkpoint

Reconstruct the fetch spine without the diagram. There is no answer bank.

Fill in the blanks4 marks
PC begins at 410 and memory location 410 contains instruction Z. Immediately after fetch, MAR contains checkpoint gap 1, CIR contains checkpoint gap 2, and PC contains checkpoint gap 3. The operation described by instruction Z happens later, during the checkpoint gap 4.

Consolidate your understanding

Reconstruct the fetch sequence once more without the diagram, naming every register, bus and transferred value.