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OCR H446 1.1.1 Data, address and control buses

Part 3 of 12 · H446 1.1.1 · Structure and function of the processor

Bus questions in OCR H446 1.1.1 are marked on what each set of lines carries and in which direction, not on naming three buses. This worksheet builds the address, data and control model on a worked memory read, then asks students to turn the same model round for a write.

Students will:

  • state what the address, data and control buses each carry
  • connect the memory address register and memory data register to the bus that serves each
  • trace a memory read from the address leaving the processor to the value arriving back
  • describe the direction of travel on each bus during a memory write
  • explain the part two named buses play in a supplied transfer

Inside: 5 explanation cells, 1 multiple-choice question, 2 fill-in-the-blanks cells and 2 written answers. 15 marks, about 20 to 25 minutes.

Series: H446 1.1.1 · Structure and function of the processor, part 3 of 12.

Shared by Coding PathwayVerified teacher

  • 10 cells
  • About 30 minutes
  • CC BY-SA 4.0
  • Shared 31 Aug 2026
  • Updated 15 Sept 2026

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The whole resource, exactly as a class sees it. Answers and marking are held back.

Data, address and control buses

A Central Processing Unit (CPU) must communicate with memory and input/output devices. A bus is a collection of communication lines with a particular purpose.

By the end, you will be able to

  • state exactly what each bus carries;
  • connect the Memory Address Register and Memory Data Register to the correct bus;
  • explain rather than imply that a bus makes decisions.

What travels?

The three processor buses carry different thingsCPUmemory / I/Oaddress bus: location to accessdata bus: data or instructionscontrol bus: read, write, clock and other control signalsA bus is a communication path. Signals coordinate components; the bus does not make decisions.

The address bus carries the location to access, commonly from the CPU. The data bus carries data and instructions between components and is generally bidirectional. The control bus carries signals such as read, write, clock and interrupt signals. Those signals coordinate actions; the physical bus is only the route.

The Memory Address Register (MAR) supplies the address for a memory access. The Memory Data Register (MDR) holds the data or instruction transferred during that access.

Worked memory read

If the Memory Address Register (MAR) holds 240, the address bus carries 240. The Control Unit (CU) sends a read signal on the control bus. The contents of memory location 240 travel back on the data bus and are held in the Memory Data Register (MDR).

A complete answer to a bus-purpose question names both what is carried and where it travels.

Multiple choice1 mark

Which statement is incorrect?

  • AThe control bus carries signals used to coordinate operations
  • BThe data bus can carry an instruction from memory
  • CThe control bus itself decides which instruction to execute
  • DThe address bus carries a memory location
Fill in the blanks3 marks
For a memory read, the location travels on the gap 1, the read signal travels on the gap 2, and the returned contents travel on the gap 3.
  • address bus
  • control bus
  • data bus
  • ALU
Written answer3 marks

Describe the purpose of the data bus, address bus and control bus.

Write one precise sentence for each bus. Include what it carries.

Students type their answer here.

Written answer4 marks

MAR holds 500 and MDR later holds the instruction stored there. Explain the role of two buses in this transfer.

Name each bus and the value/signal it carries.

Students type their answer here.

Checkpoint

Apply the same bus model to a memory write, changing the direction from the worked read. Complete it from memory without an answer bank.

Fill in the blanks4 marks
During a memory write, MAR holds 640 and MDR holds 27. The address bus carries checkpoint gap 1, the control bus carries a checkpoint gap 2, and the data bus carries checkpoint gap 3 towards memory. The CU coordinates the action; each bus only checkpoint gap 4 its value or signal.

Consolidate your understanding

Check that each bus is described by what it carries, with the correct source, destination and direction.