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OCR H446 1.1.1 Processor structure and function exam transition
Part 10 of 12 · H446 1.1.1 · Structure and function of the processor
This is the assessment piece for OCR H446 1.1.1, intended to be sat closed-book rather than taught from. Its original questions sample the whole specification row, running from register precision and a full fetch description to an extended evaluation of processor design choices for a live audio device.
Students will:
- answer processor questions with precise terminology under examination conditions
- describe a fetch from a stated address and give the resulting register contents
- explain how decode and execute change the processor when a branch condition is true
- write one qualified account covering clock speed, cores and cache together
- evaluate architecture, cache and pipelining choices for a low delay device on a moderate budget
Inside: 2 explanation cells, 1 multiple-choice question and 9 written answers. 47 marks, about 55 to 70 minutes.
Series: H446 1.1.1 · Structure and function of the processor, part 10 of 12.
Shared by Coding PathwayVerified teacher
- 12 cells
- About 60 minutes
- CC BY-SA 4.0
- Shared 31 Aug 2026
- Updated 15 Sept 2026
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The whole resource, exactly as a class sees it. Answers and marking are held back.
Processor structure and function: examination transition
Complete this worksheet closed-book and without checking answers as you go. It samples the whole specification row using original questions based on recurring examination demands.
Use precise terminology and scenario detail. Explain how each effect occurs, show each state change and compare the same feature on both sides.
Which register normally receives the contents returned from memory before an instruction is copied to the CIR?
- APC
- BMAR
- CMDR
- DACC
Describe the roles of the CU and ALU in processing an instruction.
Write distinct actions for both components.
Students type their answer here.
Describe the purpose of the data bus, address bus and control bus.
State what each bus carries.
Students type their answer here.
A byte-addressable memory uses a 15-bit address bus. Calculate its maximum directly addressable capacity in bytes and KiB.
Show the power of two, give the number of addresses and keep units in the answer.
Students type their answer here.
PC = 720 and memory location 720 contains instruction Q. Describe the fetch stage and state the resulting PC and CIR contents.
Give an ordered sequence involving registers and buses. The meaning of instruction Q is not needed during fetch.
Students type their answer here.
Instruction Q means ‘branch to address 850 if the last result was zero’. The zero condition is true. Explain how decode and execute affect the processor before the next fetch.
Name the CU, condition and PC effect. The low-level meaning is supplied.
Students type their answer here.
Explain how higher clock speed, more cores and a larger/faster cache may affect processor performance.
For every factor include direction, mechanism and a qualification where relevant.
Students type their answer here.
Explain processor pipelining and one reason its ideal performance gain may not be achieved.
Distinguish throughput from the time for one instruction.
Students type their answer here.
Compare two differences between Von Neumann and Harvard architectures.
Use one matched comparison per paragraph.
Students type their answer here.
A live audio device must process a continuous stream with low delay. It has a moderate budget. Evaluate processor design choices involving architecture, cache and pipelining.
Apply competing effects and reach a supported, conditional conclusion.
Students type their answer here.
Review your responses
Check that every comparison states both designs, every performance claim explains why, and each register is described by its contents. Check every capacity answer identifies the addressable unit and includes units. Check every fetch or branch response for explicit state changes, and do not assume that doubling a processor feature doubles performance.